Clock signal generation is a critical function in many digital and mixed-signal circuits as achieving high performance in such systems often requires a clock with precise phase position. Examples of such systems are phase-locked loops and delay-locked loops, clock and data recovery circuits, time-interleaved analog to digital converters (ADCs) etc. Phase interpolators are often used to generate an output clock with an adjustable phase from two input clock signals. Phase interpolators typically use digital control bits to determine the phase of the output clock that is a weighted sum of the phases of the two input clocks.
Traditionally, interpolators with high phase resolution have been implemented using current mode logic (CML) circuits. In particular, with a standard CML-type interpolator, two input clocks are first pre-conditioned using a slew-rate limiting circuit, and then input to an interpolator core that interpolates the phases of the two slew-rate limited input clock signals. The interpolation between the two slew-rate limited input clock phases is determined by the relative magnitudes of tail currents of the CML circuit, which can be set with current-mode digital to analog converters (DACs). High phase resolution in the interpolation can be achieved in a straightforward manner by employing high-resolution DACs.
A CML phase interpolator is a convenient choice when clock signals in the system are distributed with CML levels. In more recent systems, such as high-speed I/O macros, CMOS (rail-to-rail) clock distribution is employed instead of CML clock distribution, to improve power efficiency. In this case, the use of CML phase interpolators necessitates CMOS-to-CML converters in front of the interpolator, and CML-to-CMOS converters in back of the interpolator. Furthermore, pre-conditioning slew-rate-limiters may also be used to maintain good linearity in the interpolation. The complexity of all these additional circuits increases the circuit costs (e.g., chip area, power), reducing the attractiveness of a CML phase interpolator solution.
For these reasons, it is desirable to have a phase interpolator that directly operates on and produces CMOS rail-to-rail clock signals. A simple CMOS phase interpolator can be implemented by dotting together the outputs of a plurality of CMOS inverters driven by different clock phases. In this circuit implementation, two input clock phases are fed to multiple tri-state inverters of varying strengths, which are turned on or off using n-bit control words. The sum of these control words can be held constant, wherein the output clock phase depends on the relative values of these control words.
Typically, the interpolation linearity achieved with a CMOS interpolator is not as good as the interpolation linearity achieved with a CML phase interpolator, especially if the input phases are relatively widely spaced, such as 90 degrees or more. Furthermore, it is difficult to achieve high phase resolution with CMOS interpolators. Indeed, since the area and power considerations usually limit the number of inverters that can be switched in, the quantization of the resulting interpolation is relatively coarse.